EPM5192AGC vs EPM5192AGC-15 Comparaison
Comparaison détaillée côte à côte de EPM5192AGC par Altera et EPM5192AGC-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AGC | EPM5192AGC-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $56,00 | $27,80 |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | — |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | — |
| Architecture | CMOS, sum-of-products with macrocell output logic | — |
| Process Technology | CMOS | — |
| Boîtier | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | Ceramic Pin Grid Array (PGA) |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | — |
| Security Bit | Programmable security bit (per MAX 5000 family) | — |
| Tension d'alimentation | [DATA_NEEDED: VCC nominal and tolerance] | — |
| Type de montage | Through-hole (Pin Grid Array) | — |
| Statut RoHS | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | — |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | MAX 5000 |
| Logic Array Blocks | — | 16 (typical for 192-macrocell MAX 5000) |
| Maximum User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Total Inputs | — | 72 |
| Propagation Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | UV erase + EPROM program (via Altera programmer) |
| Statut du cycle de vie | — | Obsolete / Last Time Buy (per Altera legacy product list) |