EPM5192AGC vs EPM5192AGC-15 对比

详细并排对比 EPM5192AGC 出自 Altera 和 EPM5192AGC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AGC EPM5192AGC-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $56.00 $27.80
Family MAX 5000 (High-Speed, High-Density MAX 5000 Devices) —
Device Type UV-Erasable / OTP Complex PLD (EPLD) —
Macrocells 192 192
Logic Density High-density (per MAX 5000 family definition) —
Architecture CMOS, sum-of-products with macrocell output logic —
Process Technology CMOS —
封装 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) Ceramic Pin Grid Array (PGA)
Speed Grade Suffix C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) —
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Programmability UV-erasable (windowed package) / One-Time-Programmable (windowless variant) —
Security Bit Programmable security bit (per MAX 5000 family) —
电源电压 [DATA_NEEDED: VCC nominal and tolerance] —
安装类型 Through-hole (Pin Grid Array) —
RoHS 状态 Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant]
Lifecycle Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) —
Programming Support MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers —
Product Type — EPLD (Erasable Programmable Logic Device)
Series — MAX 5000
Logic Array Blocks — 16 (typical for 192-macrocell MAX 5000)
Maximum User I/O Pins — 64
Dedicated Inputs — 7
Total Inputs — 72
Propagation Delay (tPD) — 15 ns (pin-to-pin, -15 speed grade)
Supply Voltage (VCC) — 5 V
Technology — CMOS, UV-erasable EPROM
Programming Method — UV erase + EPROM program (via Altera programmer)
生命周期状态 — Obsolete / Last Time Buy (per Altera legacy product list)

数据手册与资源

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