EPM5192AGC vs EPM5192AGC84-20 Comparaison
Comparaison détaillée côte à côte de EPM5192AGC par Altera et EPM5192AGC84-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AGC | EPM5192AGC84-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $56,00 | $41,20 |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | — |
| Architecture | CMOS, sum-of-products with macrocell output logic | — |
| Process Technology | CMOS | CMOS |
| Boîtier | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | — |
| Security Bit | Programmable security bit (per MAX 5000 family) | — |
| Tension d'alimentation | [DATA_NEEDED: VCC nominal and tolerance] | [DATA_NEEDED: VCC range] |
| Type de montage | Through-hole (Pin Grid Array) | Through-Hole (Pin Grid Array socket) |
| Statut RoHS | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | — |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | — |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Operating Temperature Grade | — | Commercial |
| I/O Standard | — | 5V CMOS / TTL compatible |