EPM5192AJC84-15 vs EPM5192AGC84-15 Comparaison
Comparaison détaillée côte à côte de EPM5192AJC84-15 par Altera et EPM5192AGC84-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 Obsolete
Comparaison des spécifications
| Paramètre | EPM5192AJC84-15 | EPM5192AGC84-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,95 | $42,00 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable/OTP Complex PLD |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | — |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.5 V to 5.5 V |
| Technology | CMOS, UV-erasable EPROM | — |
| Boîtier | 84-pin PLCC (J84C) windowed ceramic | 84-pin Ceramic PGA (Pin Grid Array) |
| Type de montage | Surface Mount | Through-Hole |
| Température de fonctionnement | [DATA_NEEDED: commercial/industrial/military grade] | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] |
| Programming Method | UV-erase + EPROM programming (windowed package) | — |
| Logic Blocks | 16 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Statut RoHS | Non-compliant (contains Pb, ceramic windowed package) | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] |
| Process Technology | CMOS EPROM | CMOS |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Internal Clock Frequency | — | 83.3 MHz |
| Programmable Element | — | UV-Erasable EPROM cell |