EPM5192AJI84-15 vs EPM5192AGC84-15 Comparaison
Comparaison détaillée côte à côte de EPM5192AJI84-15 par Altera et EPM5192AGC84-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AJI84-15 | EPM5192AGC84-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $27,80 | $42,00 |
| Device Family | MAX 5000 EPLD | — |
| Product Type | UV-Erasable / OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 16 | 12 |
| User I/O Pins | 84 | 64 |
| Propagation Delay (tPD) | 15 ns | 15 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | 4.5 V to 5.5 V |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS |
| Package Type | 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window | — |
| Type de montage | Through-Hole (SMD socket-compatible) | Through-Hole |
| Température de fonctionnement | -40 °C to +85 °C (Industrial, 'I' suffix) | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] |
| Programming Method | UV erase + EPROM program via standard Altera programmer | — |
| Design Tool Support | MAX+PLUS II (legacy); not supported by modern Quartus Prime | — |
| Statut RoHS | unknown | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] |
| Lead-Free | unknown | — |
| Sans halogène | unknown | — |
| Functional Equivalent (Plastic OTP) | EPM5192AJC84-15 (windowless plastic JLCC, same die) | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-Erasable/OTP Complex PLD |
| Dedicated Inputs | — | 7 |
| Maximum Internal Clock Frequency | — | 83.3 MHz |
| Programmable Element | — | UV-Erasable EPROM cell |
| Boîtier | — | 84-pin Ceramic PGA (Pin Grid Array) |