EPM5192AQC100-20 vs EPM5192AQM100-20 Comparaison
Comparaison détaillée côte à côte de EPM5192AQC100-20 par Altera et EPM5192AQM100-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteComparaison des spécifications
| Paramètre | EPM5192AQC100-20 | EPM5192AQM100-20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $11,85 | $8,20 |
| Device Family | MAX 5000 | MAX 5000 (EPLD / classic CPLD) |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 192 | — |
| Maximum Operating Frequency | 66.7 MHz | — |
| Propagation Delay (tpd) | 33 ns | — |
| Boîtier | 100-lead PQFP (R-PQFP-G100) | 100-pin PQFP (JESD-30 code R-PQFP-G100) |
| Terminal Pitch | 0.65 mm | — |
| Process Technology | CMOS | CMOS EPROM-based |
| Programming Technology | UV-Erasable / One-Time-Programmable (OTP) | — |
| Tension d'alimentation | 5 V (typical, MAX 5000 family) | [DATA_NEEDED: VCC range from datasheet] |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| I/O Count | [DATA_NEEDED: usable I/O count] | — |
| Logic Array Blocks | Multiple LABs (per MAX 5000 architecture) | — |
| Type de montage | Surface Mount (PQFP) | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: verified from manufacturer product page] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Logic Elements | — | 192 macrocells across 12 Logic Array Blocks (LABs) |
| Number of LABs | — | 12 |
| User I/O Lines | — | 64 |
| Dedicated Inputs | — | 7 |
| Pin-to-Pin Propagation Delay (tPD) | — | 33 ns |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Configuration Memory | — | On-chip EPROM (non-volatile, one-time programmable in this package) |
| Boundary-Scan Test | — | JTAG / IEEE 1149.1 compatible |
| External Clock Input | — | Yes (global clock pin) |
| Operating Temperature Grade | — | [DATA_NEEDED: explicit temperature grade from datasheet] |