EPM5192AQC100-20 vs EPM5192AQM100-20 Сравнение
Подробное сравнение бок о бок EPM5192AQC100-20 от Altera и EPM5192AQM100-20 от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteСравнение характеристик
| Параметр | EPM5192AQC100-20 | EPM5192AQM100-20 |
|---|---|---|
| Бренд | Altera | Intel |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $11,85 | $8,20 |
| Device Family | MAX 5000 | MAX 5000 (EPLD / classic CPLD) |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 192 | — |
| Maximum Operating Frequency | 66.7 MHz | — |
| Propagation Delay (tpd) | 33 ns | — |
| Корпус | 100-lead PQFP (R-PQFP-G100) | 100-pin PQFP (JESD-30 code R-PQFP-G100) |
| Terminal Pitch | 0.65 mm | — |
| Process Technology | CMOS | CMOS EPROM-based |
| Programming Technology | UV-Erasable / One-Time-Programmable (OTP) | — |
| Напряжение питания | 5 V (typical, MAX 5000 family) | [DATA_NEEDED: VCC range from datasheet] |
| Диапазон рабочих температур | [DATA_NEEDED: operating temperature range] | — |
| I/O Count | [DATA_NEEDED: usable I/O count] | — |
| Logic Array Blocks | Multiple LABs (per MAX 5000 architecture) | — |
| Тип монтажа | Surface Mount (PQFP) | Surface Mount |
| Статус RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: verified from manufacturer product page] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Уровень MSL | [DATA_NEEDED: MSL rating] | — |
| Logic Elements | — | 192 macrocells across 12 Logic Array Blocks (LABs) |
| Number of LABs | — | 12 |
| User I/O Lines | — | 64 |
| Dedicated Inputs | — | 7 |
| Pin-to-Pin Propagation Delay (tPD) | — | 33 ns |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Configuration Memory | — | On-chip EPROM (non-volatile, one-time programmable in this package) |
| Boundary-Scan Test | — | JTAG / IEEE 1149.1 compatible |
| External Clock Input | — | Yes (global clock pin) |
| Operating Temperature Grade | — | [DATA_NEEDED: explicit temperature grade from datasheet] |