EPM5192AQM100-20 vs EPM5192AQC100-15 Comparaison
Comparaison détaillée côte à côte de EPM5192AQM100-20 par Intel et EPM5192AQC100-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteComparaison des spécifications
| Paramètre | EPM5192AQM100-20 | EPM5192AQC100-15 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,20 | $9,95 |
| Device Family | MAX 5000 (EPLD / classic CPLD) | — |
| Logic Elements | 192 macrocells across 12 Logic Array Blocks (LABs) | — |
| Number of LABs | 12 | — |
| User I/O Lines | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Pin-to-Pin Propagation Delay (tPD) | 33 ns | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Boîtier | 100-pin PQFP (JESD-30 code R-PQFP-G100) | 100-pin PQFP (R-PQFP-G100) |
| Type de montage | Surface Mount | Surface Mount |
| Process Technology | CMOS EPROM-based | — |
| Configuration Memory | On-chip EPROM (non-volatile, one-time programmable in this package) | EPROM (UV-erasable, OTP) |
| Boundary-Scan Test | JTAG / IEEE 1149.1 compatible | — |
| External Clock Input | Yes (global clock pin) | — |
| Operating Temperature Grade | [DATA_NEEDED: explicit temperature grade from datasheet] | — |
| Tension d'alimentation | [DATA_NEEDED: VCC range from datasheet] | — |
| Statut RoHS | [DATA_NEEDED: verified from manufacturer product page] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Altera (now Intel) |
| Family | — | MAX 5000 |
| Device Type | — | UV-Erasable / OTP Complex PLD (CPLD) |
| Technology | — | CMOS |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Propagation Delay (tPD) | — | 25 ns (-15 speed grade) |
| Total Inputs | — | 72 |
| User I/O Pins | — | 64 |
| External Clock Inputs | — | 1 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |