EPM5192GC1 vs EPM5192JC1 Comparaison
Comparaison détaillée côte à côte de EPM5192GC1 par Altera et EPM5192JC1 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192GC1 | EPM5192JC1 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $24,50 | $48,30 |
| Family | MAX 5000 | MAX 5000 (MAX 5xxx CPLD) |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 192 | 192 |
| Usable Gates | 3,750 | 3750 |
| Maximum Operating Frequency | 62.5 MHz | 62.5 MHz |
| Supply Voltage (VCC) | 5 V | 5 V (nominal) |
| Programming Technology | UV-Erasable / OTP EPROM | — |
| Package Type | Ceramic PGA (Pin Grid Array) | — |
| Logic Elements | 192 macrocells with AND/OR array | — |
| Process Technology | EPROM-based CMOS | 0.5 µm CMOS, UV-erasable EPROM |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temp range] |
| Propagation Delay | [DATA_NEEDED: tpd specification] | — |
| Nombre de broches | [DATA_NEEDED: pin count for GC1 PGA package] | — |
| Type de montage | Through-hole (PGA) | [DATA_NEEDED: surface mount or through-hole] |
| Statut RoHS | unknown | unknown |
| Development Tool | Altera MAX+PLUS II | — |
| Manufacturer | — | Intel (formerly Altera Corporation) |
| Propagation Delay (typ) | — | [DATA_NEEDED: propagation delay in ns] |
| I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Boîtier | — | [DATA_NEEDED: exact package from datasheet] |
| Programming Interface | — | JTAG-compatible (Altera MAX 5xxx) |
| Logic Blocks (LABs) | — | 24 (8 macrocells per LAB) |
| AEC-Q100 | — | not_applicable |
| Lifecycle | — | Obsolete - last-time-buy stock only at franchised distributors |