EPM5192GC1 vs EPM5192JC1 比較
詳細な並列比較: EPM5192GC1 メーカー: Altera および EPM5192JC1 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192GC1 | EPM5192JC1 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $24.50 | $48.30 |
| Family | MAX 5000 | MAX 5000 (MAX 5xxx CPLD) |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 192 | 192 |
| Usable Gates | 3,750 | 3750 |
| Maximum Operating Frequency | 62.5 MHz | 62.5 MHz |
| Supply Voltage (VCC) | 5 V | 5 V (nominal) |
| Programming Technology | UV-Erasable / OTP EPROM | — |
| Package Type | Ceramic PGA (Pin Grid Array) | — |
| Logic Elements | 192 macrocells with AND/OR array | — |
| Process Technology | EPROM-based CMOS | 0.5 µm CMOS, UV-erasable EPROM |
| 動作温度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temp range] |
| Propagation Delay | [DATA_NEEDED: tpd specification] | — |
| ピン数 | [DATA_NEEDED: pin count for GC1 PGA package] | — |
| 実装タイプ | Through-hole (PGA) | [DATA_NEEDED: surface mount or through-hole] |
| RoHS ステータス | unknown | unknown |
| Development Tool | Altera MAX+PLUS II | — |
| Manufacturer | — | Intel (formerly Altera Corporation) |
| Propagation Delay (typ) | — | [DATA_NEEDED: propagation delay in ns] |
| I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| パッケージ | — | [DATA_NEEDED: exact package from datasheet] |
| Programming Interface | — | JTAG-compatible (Altera MAX 5xxx) |
| Logic Blocks (LABs) | — | 24 (8 macrocells per LAB) |
| AEC-Q100 | — | not_applicable |
| Lifecycle | — | Obsolete - last-time-buy stock only at franchised distributors |