EPM5192GM-2 vs EPM5192GM Comparaison
Comparaison détaillée côte à côte de EPM5192GM-2 par Intel et EPM5192GM par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192GM-2 | EPM5192GM |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $92,00 | $58,00 |
| Family | Altera MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (PLD) |
| Macrocell Count | 192 | — |
| Logic Elements | [DATA_NEEDED: logic element count for MAX 5000 family] | — |
| Propagation Delay (tPD) | 55 ns | — |
| Speed Grade | -2 | — |
| Process Technology | CMOS | — |
| Programmability | UV-erasable (windowed package) | — |
| Boîtier | PGA-84 (Ceramic Pin Grid Array, windowed) | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| Nombre de broches | 84 | — |
| Type de montage | Through-hole (PGA socket) | Through-Hole (PGA) |
| Température de fonctionnement | [DATA_NEEDED: military/industrial grade temperature range] | [DATA_NEEDED: commercial/industrial/military grade] |
| Tension d'alimentation | [DATA_NEEDED: VCC nominal, typically 5 V for MAX 5000] | [DATA_NEEDED: typical VCC range] |
| Statut RoHS | [DATA_NEEDED: ceramic PGA with UV window is typically non-RoHS - verify with manufacturer] | Non-compliant (contains lead in ceramic PGA) |
| Datasheet Page Count | 52 | — |
| Product Family | — | MAX 5000 |
| Technology | — | CMOS |
| Number of Macrocells | — | 192 |
| Usable Gates | — | 3,750 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | — | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | — | 55 ns |
| Erasure Method | — | UV (windowed ceramic package) |
| Maximum User I/O | — | [DATA_NEEDED: exact I/O count for CPGA-84] |
| Process Node | — | [DATA_NEEDED: CMOS process geometry] |
| Programming Interface | — | JTAG-compatible (per MAX 5000 family) |