EPM5192JC-ES vs EPM5192JC-1 Comparaison
Comparaison détaillée côte à côte de EPM5192JC-ES par Intel et EPM5192JC-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192JC-ES | EPM5192JC-1 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $16,45 | $22,40 |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | CPLD - Complex Programmable Logic Device |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | UV-EPROM (erasable under UV lamp) |
| Boîtier | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | — |
| Type de montage | Surface Mount | — |
| Technology | CMOS | CMOS, UV-Erasable / OTP |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range for ES grade] | 0 C to +70 C (commercial) |
| Tension d'alimentation | [DATA_NEEDED: VCC nominal] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | 84 |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Family | — | MAX 5000 |
| Usable Gates | — | 3750 |
| Propagation Delay (tPD) | — | 40 ns (speed grade -1) |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Package Type | — | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| JEDEC Package Code | — | S-CQCC-J84 |
| Programming Interface | — | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Process | — | CMOS EPROM |
| I/O Standard | — | TTL/CMOS 5 V compatible |