EPM5192JC-ES vs EPM5192JC-1 Comparação
Comparação detalhada lado a lado de EPM5192JC-ES por Intel e EPM5192JC-1 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM5192JC-ES | EPM5192JC-1 |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $16,45 | $22,40 |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | CPLD - Complex Programmable Logic Device |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | UV-EPROM (erasable under UV lamp) |
| Encapsulamento | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | — |
| Tipo de montagem | Surface Mount | — |
| Technology | CMOS | CMOS, UV-Erasable / OTP |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| Temperatura de operação | [DATA_NEEDED: operating temperature range for ES grade] | 0 C to +70 C (commercial) |
| Tensão de alimentação | [DATA_NEEDED: VCC nominal] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | 84 |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Nível MSL | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Family | — | MAX 5000 |
| Usable Gates | — | 3750 |
| Propagation Delay (tPD) | — | 40 ns (speed grade -1) |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Package Type | — | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| JEDEC Package Code | — | S-CQCC-J84 |
| Programming Interface | — | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Process | — | CMOS EPROM |
| I/O Standard | — | TTL/CMOS 5 V compatible |