EPM5192JC1 vs EPM5192GC1 Comparaison
Comparaison détaillée côte à côte de EPM5192JC1 par Intel et EPM5192GC1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192JC1 | EPM5192GC1 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $48,30 | $24,50 |
| Family | MAX 5000 (MAX 5xxx CPLD) | MAX 5000 |
| Manufacturer | Intel (formerly Altera Corporation) | — |
| Macro Cells | 192 | 192 |
| Usable Gates | 3750 | 3,750 |
| Maximum Operating Frequency | 62.5 MHz | 62.5 MHz |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V |
| Process Technology | 0.5 µm CMOS, UV-erasable EPROM | EPROM-based CMOS |
| Propagation Delay (typ) | [DATA_NEEDED: propagation delay in ns] | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Boîtier | [DATA_NEEDED: exact package from datasheet] | — |
| Type de montage | [DATA_NEEDED: surface mount or through-hole] | Through-hole (PGA) |
| Température de fonctionnement | [DATA_NEEDED: operating temp range] | [DATA_NEEDED: operating temperature range] |
| Programming Interface | JTAG-compatible (Altera MAX 5xxx) | — |
| Logic Blocks (LABs) | 24 (8 macrocells per LAB) | — |
| Statut RoHS | unknown | unknown |
| AEC-Q100 | not_applicable | — |
| Lifecycle | Obsolete - last-time-buy stock only at franchised distributors | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programming Technology | — | UV-Erasable / OTP EPROM |
| Package Type | — | Ceramic PGA (Pin Grid Array) |
| Logic Elements | — | 192 macrocells with AND/OR array |
| Propagation Delay | — | [DATA_NEEDED: tpd specification] |
| Nombre de broches | — | [DATA_NEEDED: pin count for GC1 PGA package] |
| Development Tool | — | Altera MAX+PLUS II |