EPM5192JI vs EPM5192GI Comparaison
Comparaison détaillée côte à côte de EPM5192JI par Altera et EPM5192GI par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192JI | EPM5192GI |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $18,95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-erasable CMOS Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 16 (12 macrocells per LAB) |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tpd) | 55 ns | — |
| Tension d'alimentation | 4.75 V to 5.25 V (nominal 5 V) | — |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM (UV-erasable / OTP) |
| Boîtier | 84-pin PLCC (windowed, J-suffix ceramic) | — |
| Température de fonctionnement | -40 C to +125 C (industrial, I-suffix) | -40 C to +85 C (Industrial) |
| Type de montage | Surface Mount (PLCC socket recommended for UV erasure) | Through-hole (PGA) |
| Statut RoHS | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] | [DATA_NEEDED: not confirmed in verified web data] |
| Programming Method | Altera MAX 5000 programming algorithm (device programmer) | — |
| Erasure Method | UV exposure through windowed package | — |
| Total Inputs | — | 72 |
| Propagation Delay (tPD) | — | 55 ns |
| Maximum Internal Frequency (fCNT) | — | 33.3 MHz |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Package Type | — | 84-pin PGA (Pin Grid Array), ceramic with quartz window |
| Programmable | — | UV-erasable (windowed) and OTP variants |