EPM5192LC-M205A vs EPM5192JC Comparaison
Comparaison détaillée côte à côte de EPM5192LC-M205A par Altera et EPM5192JC par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192LC-M205A | EPM5192JC |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $23,75 | $16,40 |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Dedicated Inputs | 7 | — |
| I/O Pins | 64 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EPROM (UV-erasable / OTP) | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Global Clock Inputs | 1 | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: commercial / industrial / military grade] |
| Package Type | 205-pin (M205A) | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: original Altera marking not RoHS] |
| Configuration Memory | UV-erasable / OTP EPROM | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Boîtier | — | 68-pin PLCC (JC) windowed ceramic |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Tension d'alimentation | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |