EPM570T144C5N vs EPM1270T144C5N Comparaison
Comparaison détaillée côte à côte de EPM570T144C5N par Intel et EPM1270T144C5N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM1270T144C5N - MAX II CPLD, 980 LEs, 212 I/O, TQFP-144 | Intel/Altera
EPM1270T144C5N ✓ ActifComparaison des spécifications
| Paramètre | EPM570T144C5N | EPM1270T144C5N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,35 | $19,75 |
| Family | MAX II | MAX II |
| Series | MAX II Device | — |
| Logic Elements (LEs) | 570 | 1270 |
| Macrocells | 440 | — |
| User I/Os | 116 | — |
| Internal User Flash Memory | 8 Kbit | — |
| Global Clocks | 4 | — |
| Process Technology | 0.18 µm 6-layer-metal flash | 0.18 µm |
| Core Voltage (VCCINT) | 1.8 V (typical, internally regulated) | — |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank) | — |
| Maximum User I/O Pins | 116 | — |
| Propagation Delay (tPD) | 5.5 ns (typical, [DATA_NEEDED: exact speed grade]) | 6.2 ns |
| Maximum Frequency (fMAX) | 201.1 MHz | — |
| Température de fonctionnement | 0 °C to +85 °C (commercial, C5 grade) | 0 °C to +85 °C (Commercial) |
| Boîtier | TQFP-144 (20 × 20 mm, 0.5 mm pitch) | TQFP-144 (T144), 22 x 22 mm, 0.5 mm pitch |
| Type de montage | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | JTAG (IEEE 1149.1), In-System Programmable |
| Configuration Storage | On-chip non-volatile flash | — |
| Supported I/O Standards | LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO) | — |
| Statut RoHS | Compliant | Compliant (lead-free) |
| Lead-Free | Yes | — |
| Niveau MSL | 3 (per JEDEC J-STD-020) | — |
| Design Software | Intel Quartus II (MAX II device support) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 980 |
| Maximum User I/Os | — | 212 |
| Number of Logic Array Blocks (LABs) | — | 127 |
| Maximum Internal Frequency | — | 201.1 MHz |
| Supply Voltage (Core) | — | 2.5 V / 3.3 V |
| Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | — | -5 |
| Configuration Memory | — | Internal flash (non-volatile, instant-on) |
| Sans halogène | — | Compliant |