EPM7128AETC100-10N vs EPM7128AETI100-7 Comparaison
Comparaison détaillée côte à côte de EPM7128AETC100-10N par Intel et EPM7128AETI100-7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteAltera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteComparaison des spécifications
| Paramètre | EPM7128AETC100-10N | EPM7128AETI100-7 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $30,10 |
| Family | MAX 7000AE | MAX 7000A |
| Series | EPM7128AE | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Usable Gates | 2500 | 2,500 |
| Logic Array Blocks | 16 | — |
| User I/Os | 84 | 84 |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Tolerance | 5.0 V tolerant | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 7.5 ns |
| Speed Grade | -10 | — |
| Maximum Frequency | [DATA_NEEDED: maximum toggle frequency] | — |
| Boîtier | TQFP-100 | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) |
| Type de montage | Surface Mount | Surface Mount |
| Programming | JTAG (IEEE 1149.1) ISP / EEPROM | — |
| Température de fonctionnement | 0C to +70C (commercial) | -40 C to +85 C (Industrial) |
| Lead-Free / RoHS | Yes (N suffix) | — |
| Process Technology | CMOS EEPROM | — |
| Architecture | Multiple Array MatriX (MAX) - 2nd generation | — |
| PCI Compliance | Yes (33 MHz, -10 grade per PCI SIG 2.2) | — |
| Logic Blocks (LABs) | — | 8 |
| Maximum Counter Frequency | — | 129.9 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Bank Supply (VCCIO) | — | 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Global Clock Inputs | — | 4 dedicated |
| Statut RoHS | — | [DATA_NEEDED: confirm RoHS for non-N suffix] |
| Lead-Free Version (MPN Suffix) | — | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) |