EPM7128AETC100-10N vs EPM7128AETI100-7 Comparison

Detailed side-by-side comparison of EPM7128AETC100-10N by Intel and EPM7128AETI100-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7128AETC100-10N EPM7128AETI100-7
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $30.10
Family MAX 7000AE MAX 7000A
Series EPM7128AE β€”
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 128 128
Usable Gates 2500 2,500
Logic Array Blocks 16 β€”
User I/Os 84 84
Supply Voltage (Core) 3.3 V β€”
I/O Tolerance 5.0 V tolerant β€”
Pin-to-Pin Delay (tPD) 10 ns 7.5 ns
Speed Grade -10 β€”
Maximum Frequency [DATA_NEEDED: maximum toggle frequency] β€”
Package TQFP-100 100-pin TQFP (1.0 mm pitch, 14 x 14 mm)
Mounting Type Surface Mount Surface Mount
Programming JTAG (IEEE 1149.1) ISP / EEPROM β€”
Operating Temperature 0C to +70C (commercial) -40 C to +85 C (Industrial)
Lead-Free / RoHS Yes (N suffix) β€”
Process Technology CMOS EEPROM β€”
Architecture Multiple Array MatriX (MAX) - 2nd generation β€”
PCI Compliance Yes (33 MHz, -10 grade per PCI SIG 2.2) β€”
Logic Blocks (LABs) β€” 8
Maximum Counter Frequency β€” 129.9 MHz
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Bank Supply (VCCIO) β€” 2.5 V / 3.3 V / 5 V (MultiVolt)
Configuration Memory β€” EEPROM (non-volatile, in-system programmable)
JTAG Support β€” Yes (IEEE 1149.1 boundary-scan)
Global Clock Inputs β€” 4 dedicated
RoHS Status β€” [DATA_NEEDED: confirm RoHS for non-N suffix]
Lead-Free Version (MPN Suffix) β€” -N suffix denotes lead-free (e.g., EPM7128AETI100-7N)

Datasheets & Resources

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