EPM7128AETI100-7 vs EPM7128ATI100-10 Comparaison
Comparaison détaillée côte à côte de EPM7128AETI100-7 par Altera et EPM7128ATI100-10 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteAltera
EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A
EPM7128ATI100-10 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM7128AETI100-7 | EPM7128ATI100-10 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $30,10 | $13,85 |
| Family | MAX 7000A | MAX 7000A (MAX II of MAX 7000 series) |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | — |
| Logic Blocks (LABs) | 8 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Counter Frequency | 129.9 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Global Clock Inputs | 4 dedicated | — |
| Boîtier | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) | 100-pin TQFP (14x14 mm) |
| Température de fonctionnement | -40 C to +85 C (Industrial) | -40C to +85C (Industrial, 'I' suffix) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: confirm RoHS for non-N suffix] | Non-compliant (legacy part) |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) | — |
| Series | — | MAX 7000A |
| Programmable Type | — | EE PLD (EEPROM-based, in-system programmable) |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| Number of I/O Pins | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Standard | — | MultiVolt (2.5V / 3.3V / 5.0V tolerant) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG (ISP) |
| Process Technology | — | CMOS EEPROM |