EPM7128AETI100-7 vs EPM7128ATI100-10 比較
詳細な並列比較: EPM7128AETI100-7 メーカー: Altera および EPM7128ATI100-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteAltera
EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A
EPM7128ATI100-10 ⚠ ラストタイムバイ仕様比較
| パラメータ | EPM7128AETI100-7 | EPM7128ATI100-10 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $30.10 | $13.85 |
| Family | MAX 7000A | MAX 7000A (MAX II of MAX 7000 series) |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | — |
| Logic Blocks (LABs) | 8 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Counter Frequency | 129.9 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Global Clock Inputs | 4 dedicated | — |
| パッケージ | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) | 100-pin TQFP (14x14 mm) |
| 動作温度 | -40 C to +85 C (Industrial) | -40C to +85C (Industrial, 'I' suffix) |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: confirm RoHS for non-N suffix] | Non-compliant (legacy part) |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) | — |
| Series | — | MAX 7000A |
| Programmable Type | — | EE PLD (EEPROM-based, in-system programmable) |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| Number of I/O Pins | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Standard | — | MultiVolt (2.5V / 3.3V / 5.0V tolerant) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG (ISP) |
| Process Technology | — | CMOS EEPROM |