EPM7128ATC100-10 vs EPM7128AETI100-7 Comparaison
Comparaison détaillée côte à côte de EPM7128ATC100-10 par Altera et EPM7128AETI100-7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 ObsoleteAltera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteComparaison des spécifications
| Paramètre | EPM7128ATC100-10 | EPM7128AETI100-7 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $4,95 | $30,10 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000A | MAX 7000A |
| Architecture | Multiple Array MatriX (MAX) | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 2.5K | 2,500 |
| User I/O Pins | 68 | — |
| Pin-to-Pin Logic Delay | 4.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Speed Grade | -10 (10 ns) | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Logic Level Support | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Program Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Boîtier | 100-pin TQFP (TC100) | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0C to +70C (commercial) | -40 C to +85 C (Industrial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: confirm RoHS for non-N suffix] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/Os | — | 84 |
| Logic Blocks (LABs) | — | 8 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Counter Frequency | — | 129.9 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Bank Supply (VCCIO) | — | 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Global Clock Inputs | — | 4 dedicated |
| Lead-Free Version (MPN Suffix) | — | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) |