EPM7256SQC208-15N vs EPM7256SRC208-10N Comparaison
Comparaison détaillée côte à côte de EPM7256SQC208-15N par Altera et EPM7256SRC208-10N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM7256SQC208-15N | EPM7256SRC208-10N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $27,20 |
| Series | MAX 7000S | — |
| Macrocells | 256 | 256 |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay | 15 ns (speed grade -15) | — |
| Tension d'alimentation | 5 V | 5.0 V |
| Boîtier | 208-pin PQFP | 208-pin RQFP (PowerQuad Flat Pack) |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| JTAG Interface | IEEE 1149.1 boundary-scan | — |
| In-System Programmability | Yes (ISP) | Yes (IEEE 1149.1 JTAG) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Statut RoHS | Lead free / RoHS Compliant | Compliant (N suffix = lead-free) |
| Logic Array Blocks | 16 macrocells per LAB | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Speed Grade | -15 | — |
| Product Category | CPLD - Complex Programmable Logic Devices | — |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Family | — | MAX 7000S |
| Usable Gates | — | 5,000 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 100 MHz |
| Logic Levels | — | 5.0 V TTL/CMOS compatible |
| Number of Logic Array Blocks | — | [DATA_NEEDED: number of LABs] |
| Maximum User Flash Memory | — | [DATA_NEEDED: user flash memory] |