EPM9320ALC84-10N vs EPM9320ALC84-10 Comparaison
Comparaison détaillée côte à côte de EPM9320ALC84-10N par Intel et EPM9320ALC84-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9320ALC84-10N | EPM9320ALC84-10 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $21,40 | $19,80 |
| Series | MAX 9000A | — |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Number of Macrocells | 320 | — |
| Number of Gates | 6,000 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 60 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency (fCNT) | 144.9 MHz | — |
| Supply Voltage (VCC) | 5.0 V nominal | — |
| Plage de température de fonctionnement | 0C to +70C (Commercial) | — |
| Programmable Technology | EEPROM (in-system programmable) | — |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Boîtier | 84-Pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (J-Lead) |
| Type de montage | Through-Hole / Socket | Surface Mount / Through-Hole (PLCC socket) |
| Part Status | Obsolete | — |
| Device | — | EPM9320 |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 52 |
| Dedicated Inputs | — | 16 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| In-System Programmability | — | 5.0 V ISP via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Température de fonctionnement | — | [DATA_NEEDED: commercial/industrial grade] |
| Statut RoHS | — | [DATA_NEEDED] |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |
| Architecture | — | MAX (Multiple Array MatriX) with FastTrack Interconnect |