EPM9320ALC84-10N vs EPM9320ALC84-10 Comparison
Detailed side-by-side comparison of EPM9320ALC84-10N by Intel and EPM9320ALC84-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALC84-10N | EPM9320ALC84-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.40 | $19.80 |
| Series | MAX 9000A | β |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Number of Macrocells | 320 | β |
| Number of Gates | 6,000 | β |
| Number of Logic Array Blocks (LABs) | 16 | β |
| User I/O Pins | 60 | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Internal Frequency (fCNT) | 144.9 MHz | β |
| Supply Voltage (VCC) | 5.0 V nominal | β |
| Operating Temperature Range | 0C to +70C (Commercial) | β |
| Programmable Technology | EEPROM (in-system programmable) | β |
| Programming Interface | JTAG (IEEE 1149.1) | β |
| Package | 84-Pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (J-Lead) |
| Mounting Type | Through-Hole / Socket | Surface Mount / Through-Hole (PLCC socket) |
| Part Status | Obsolete | β |
| Device | β | EPM9320 |
| Macrocells | β | 320 |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum User I/O Pins | β | 52 |
| Dedicated Inputs | β | 16 |
| Speed Grade | β | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Supply Voltage (VCCINT) | β | 5.0 V |
| In-System Programmability | β | 5.0 V ISP via IEEE 1149.1 JTAG |
| Technology | β | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | β | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Operating Temperature | β | [DATA_NEEDED: commercial/industrial grade] |
| RoHS Status | β | [DATA_NEEDED] |
| Non-Volatile Configuration | β | Yes (EEPROM cell, powers up in known state) |
| Architecture | β | MAX (Multiple Array MatriX) with FastTrack Interconnect |