EPM9320GC280-20 vs EPM9320GC280-15 Comparaison
Comparaison détaillée côte à côte de EPM9320GC280-20 par Altera et EPM9320GC280-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 ObsoleteComparaison des spécifications
| Paramètre | EPM9320GC280-20 | EPM9320GC280-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $67,00 | $92,50 |
| Family | MAX 9000 | MAX 9000 (EPM9320) |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 (approx.) | 6,000 |
| Logic Array Blocks (LABs) | 20 (16 macrocells each, typical for MAX 9000) | 20 (16 macrocells per LAB) |
| Maximum Operating Frequency | 100 MHz (internal counter) | — |
| Propagation Delay (tpd) | 23 ns (approx., -20 speed grade) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | — |
| JTAG Support | IEEE Std. 1149.1 compliant | — |
| Boîtier | 280-pin Ceramic Pin Grid Array (CPGA) | 280-pin Ceramic Pin Grid Array (CPGA-280) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | 0 C to +70 C (commercial) |
| Type de montage | Through-Hole (PGA socket) | Through-hole (PGA socket) |
| Statut RoHS | unknown | ROHS3 compliant (per fpgalink listing) |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Architecture | — | CMOS EEPROM-based, Multiple Array MatriX (MAX) |
| Pin-to-Pin Propagation Delay | — | 15 ns |
| Maximum Internal Frequency | — | 117.6 MHz |
| Maximum User I/O Pins | — | 164 |
| I/O Voltage Levels | — | 3.3 V or 5 V (configurable) |
| Programmability | — | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG |
| Niveau MSL | — | 3 (168 hours) |
| Technology Node | — | CMOS EEPROM, third-generation MAX |