EPM9560ABC356-10 vs EPM9560GC280-15 Comparaison
Comparaison détaillée côte à côte de EPM9560ABC356-10 par Altera et EPM9560GC280-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteComparaison des spécifications
| Paramètre | EPM9560ABC356-10 | EPM9560GC280-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $92,40 | $115,00 |
| Device Family | MAX 9000A | — |
| Product Series | MAX 9000 | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | — |
| Logic Array Blocks (LABs) | 35 | — |
| Maximum User I/Os | 216 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Tension d'alimentation | 4.75 V to 5.25 V (5 V nominal) | — |
| Programmability | EEPROM, 5-V In-System Programmable (ISP) | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| Température de fonctionnement | 0 °C to 70 °C (Commercial) | — |
| Boîtier | 356-LBGA (35 x 35 mm) | — |
| Type de montage | Surface Mount | Through-Hole |
| Statut RoHS | [DATA_NEEDED: rohs status] | Non-compliant (ceramic CPGA, contains lead) |
| Family | — | MAX 9000 |
| Device Type | — | EE PLD (CMOS EEPROM-based CPLD) |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Architecture | — | Multiple Array MatriX (MAX) |
| Statut du cycle de vie | — | Obsolete (legacy Altera MAX 9000 family) |