EPM9560ABC356-10 vs EPM9560GC280-15 对比

详细并排对比 EPM9560ABC356-10 出自 Altera 和 EPM9560GC280-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ABC356-10 EPM9560GC280-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $92.40 $115.00
Device Family MAX 9000A —
Product Series MAX 9000 —
Macrocells 560 —
Usable Gates 12,000 —
Logic Array Blocks (LABs) 35 —
Maximum User I/Os 216 —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Counter Frequency 144 MHz —
电源电压 4.75 V to 5.25 V (5 V nominal) —
Programmability EEPROM, 5-V In-System Programmable (ISP) In-System Programmable (ISP) via JTAG IEEE 1149.1
JTAG Interface IEEE Std. 1149.1 compliant —
PCI Compliance PCI Local Bus Specification Revision 2.2 —
工作温度 0 °C to 70 °C (Commercial) —
封装 356-LBGA (35 x 35 mm) —
安装类型 Surface Mount Through-Hole
RoHS 状态 [DATA_NEEDED: rohs status] Non-compliant (ceramic CPGA, contains lead)
Family — MAX 9000
Device Type — EE PLD (CMOS EEPROM-based CPLD)
Macro Cells — 560
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (tpd) — 15 ns (speed grade -15)
Propagation Delay (alternate datasheet figure) — 16.6 ns
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Technology — CMOS EEPROM, 0.5 um process (MAX third-gen)
Architecture — Multiple Array MatriX (MAX)
生命周期状态 — Obsolete (legacy Altera MAX 9000 family)

数据手册与资源

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