EPM9560ARC240-10 vs EPM9560GC280-15 Comparaison
Comparaison détaillée côte à côte de EPM9560ARC240-10 par Altera et EPM9560GC280-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteComparaison des spécifications
| Paramètre | EPM9560ARC240-10 | EPM9560GC280-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $28,80 | $115,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE PLD (CMOS EEPROM-based CPLD) |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | — |
| User I/Os (this package) | 191 (per Mouser listing) | — |
| Internal Frequency | 144.9 MHz | — |
| Propagation Delay (tpd) | 11.4 ns | 15 ns (speed grade -15) |
| Supply Voltage - Internal (VCCINT) | 5.0 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (selectable) | — |
| Process Technology | CMOS EEPROM | — |
| Boîtier | 240-pin PowerQuad QFP (RQFP / EAR240) | — |
| Température de fonctionnement | 0C to +70C (commercial) | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| Logic Family | CMOS | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic CPGA, contains lead) |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Type de montage | — | Through-Hole |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Statut du cycle de vie | — | Obsolete (legacy Altera MAX 9000 family) |