EPM9560ARC240-10 vs EPM9560GC280-15 对比

详细并排对比 EPM9560ARC240-10 出自 Altera 和 EPM9560GC280-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ARC240-10 EPM9560GC280-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $28.80 $115.00
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) EE PLD (CMOS EEPROM-based CPLD)
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX)
Usable Gates 12,000 —
Macrocells 560 —
User I/Os (this package) 191 (per Mouser listing) —
Internal Frequency 144.9 MHz —
Propagation Delay (tpd) 11.4 ns 15 ns (speed grade -15)
Supply Voltage - Internal (VCCINT) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) —
Process Technology CMOS EEPROM —
封装 240-pin PowerQuad QFP (RQFP / EAR240) —
工作温度 0C to +70C (commercial) —
Configuration Memory EEPROM (non-volatile, in-system programmable) —
Logic Family CMOS —
RoHS 状态 [DATA_NEEDED: RoHS status] Non-compliant (ceramic CPGA, contains lead)
Macro Cells — 560
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (alternate datasheet figure) — 16.6 ns
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
安装类型 — Through-Hole
Programmability — In-System Programmable (ISP) via JTAG IEEE 1149.1
Technology — CMOS EEPROM, 0.5 um process (MAX third-gen)
生命周期状态 — Obsolete (legacy Altera MAX 9000 family)

数据手册与资源

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