EPM9560GC280-15 vs EPM9560GC280-15N Comparaison
Comparaison détaillée côte à côte de EPM9560GC280-15 par Altera et EPM9560GC280-15N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteComparaison des spécifications
| Paramètre | EPM9560GC280-15 | EPM9560GC280-15N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $115,00 | $125,00 |
| Family | MAX 9000 | — |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | — |
| Macro Cells | 560 | — |
| Typical Gates | 12,000 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | 5.0 V |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | — |
| Type de montage | Through-Hole | — |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | — |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | — |
| Architecture | Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) 3rd generation |
| Statut RoHS | Non-compliant (ceramic CPGA, contains lead) | — |
| Statut du cycle de vie | Obsolete (legacy Altera MAX 9000 family) | — |
| Device Family | — | MAX 9000 |
| Product Type | — | EE PLD / CPLD |
| Macrocell Count | — | 560 |
| Usable Gates | — | 12,000 (typical) |
| Propagation Delay (tPD) | — | 16.6 ns |
| Fréquence d'horloge maximale | — | 117.6 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Logic Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (5.0-V ISP via JTAG) |
| Boundary-Scan (JTAG) | — | IEEE Std. 1149.1 compliant |
| Boîtier | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Package Code | — | PGA / CPGA280 |
| Terminal Form | — | PIN/PEG |
| Operating Temperature Grade | — | Commercial |