EPM9560GC280-15 vs EPM9560GC280-15N Comparison

Detailed side-by-side comparison of EPM9560GC280-15 by Altera and EPM9560GC280-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560GC280-15 EPM9560GC280-15N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $115.00 $125.00
Family MAX 9000 β€”
Device Type EE PLD (CMOS EEPROM-based CPLD) β€”
Macro Cells 560 β€”
Typical Gates 12,000 β€”
Maximum Operating Frequency 117.6 MHz β€”
Propagation Delay (tpd) 15 ns (speed grade -15) β€”
Propagation Delay (alternate datasheet figure) 16.6 ns β€”
Supply Voltage (VCCINT/VCCIO) 5.0 V 5.0 V
Operating Temperature (Commercial) 0C to +70C β€”
Package Type CPGA-280 (Ceramic Pin Grid Array, 280 pins) β€”
Mounting Type Through-Hole β€”
Programmability In-System Programmable (ISP) via JTAG IEEE 1149.1 β€”
Technology CMOS EEPROM, 0.5 um process (MAX third-gen) β€”
Architecture Multiple Array MatriX (MAX) Multiple Array MatriX (MAX) 3rd generation
RoHS Status Non-compliant (ceramic CPGA, contains lead) β€”
Lifecycle Status Obsolete (legacy Altera MAX 9000 family) β€”
Device Family β€” MAX 9000
Product Type β€” EE PLD / CPLD
Macrocell Count β€” 560
Usable Gates β€” 12,000 (typical)
Propagation Delay (tPD) β€” 16.6 ns
Maximum Clock Frequency β€” 117.6 MHz
Maximum Supply Voltage β€” 5.25 V
Logic Technology β€” CMOS EEPROM
In-System Programmability β€” Yes (5.0-V ISP via JTAG)
Boundary-Scan (JTAG) β€” IEEE Std. 1149.1 compliant
Package β€” CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Package Code β€” PGA / CPGA280
Terminal Form β€” PIN/PEG
Operating Temperature Grade β€” Commercial

Datasheets & Resources

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