EPM9560GC280-15 vs EPM9560GC280-15N Comparison

Detailed side-by-side comparison of EPM9560GC280-15 by Altera and EPM9560GC280-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560GC280-15 EPM9560GC280-15N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 9000 —
Device Type EE PLD (CMOS EEPROM-based CPLD) —
Macro Cells 560 —
Typical Gates 12,000 —
Maximum Operating Frequency 117.6 MHz —
Propagation Delay (tpd) 15 ns (speed grade -15) —
Propagation Delay (alternate datasheet figure) 16.6 ns —
Supply Voltage (VCCINT/VCCIO) 5.0 V 5.0 V
Operating Temperature (Commercial) 0C to +70C —
Package Type CPGA-280 (Ceramic Pin Grid Array, 280 pins) —
Mounting Type Through-Hole —
Programmability In-System Programmable (ISP) via JTAG IEEE 1149.1 —
Technology CMOS EEPROM, 0.5 um process (MAX third-gen) —
Architecture Multiple Array MatriX (MAX) Multiple Array MatriX (MAX) 3rd generation
RoHS Status Non-compliant (ceramic CPGA, contains lead) —
Lifecycle Status Obsolete (legacy Altera MAX 9000 family) —
Device Family — MAX 9000
Product Type — EE PLD / CPLD
Macrocell Count — 560
Usable Gates — 12,000 (typical)
Propagation Delay (tPD) — 16.6 ns
Maximum Clock Frequency — 117.6 MHz
Maximum Supply Voltage — 5.25 V
Logic Technology — CMOS EEPROM
In-System Programmability — Yes (5.0-V ISP via JTAG)
Boundary-Scan (JTAG) — IEEE Std. 1149.1 compliant
Package — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Package Code — PGA / CPGA280
Terminal Form — PIN/PEG
Operating Temperature Grade — Commercial

Datasheets & Resources

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