EPM9560GC280-15 vs EPM9560GC280-20N Comparaison
Comparaison détaillée côte à côte de EPM9560GC280-15 par Altera et EPM9560GC280-20N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteComparaison des spécifications
| Paramètre | EPM9560GC280-15 | EPM9560GC280-20N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $115,00 | $285,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 560 | — |
| Typical Gates | 12,000 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | — |
| Type de montage | Through-Hole | — |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | — |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | CMOS EEPROM-based |
| Architecture | Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX), 3rd generation |
| Statut RoHS | Non-compliant (ceramic CPGA, contains lead) | [DATA_NEEDED] |
| Statut du cycle de vie | Obsolete (legacy Altera MAX 9000 family) | — |
| Usable Gates | — | 6,000 to 12,000 |
| Macrocells | — | 560 |
| User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| I/O Voltage | — | 3.3 V or 5 V (configurable) |
| In-System Programmability | — | Yes (5.0-V ISP via IEEE 1149.1 JTAG) |
| Boîtier | — | 280-pin CPGA (Ceramic Pin Grid Array) |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |
| PCI Compliance | — | Yes |
| Température de fonctionnement | — | [DATA_NEEDED: industrial/commercial grade] |