EPM9560GC280-15 vs EPM9560GC280-20N Comparison

Detailed side-by-side comparison of EPM9560GC280-15 by Altera and EPM9560GC280-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560GC280-15 EPM9560GC280-20N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $115.00 $285.00
Family MAX 9000 MAX 9000
Device Type EE PLD (CMOS EEPROM-based CPLD) CPLD (Complex Programmable Logic Device)
Macro Cells 560 β€”
Typical Gates 12,000 β€”
Maximum Operating Frequency 117.6 MHz β€”
Propagation Delay (tpd) 15 ns (speed grade -15) β€”
Propagation Delay (alternate datasheet figure) 16.6 ns β€”
Supply Voltage (VCCINT/VCCIO) 5.0 V β€”
Operating Temperature (Commercial) 0C to +70C β€”
Package Type CPGA-280 (Ceramic Pin Grid Array, 280 pins) β€”
Mounting Type Through-Hole β€”
Programmability In-System Programmable (ISP) via JTAG IEEE 1149.1 β€”
Technology CMOS EEPROM, 0.5 um process (MAX third-gen) CMOS EEPROM-based
Architecture Multiple Array MatriX (MAX) Multiple Array MatriX (MAX), 3rd generation
RoHS Status Non-compliant (ceramic CPGA, contains lead) [DATA_NEEDED]
Lifecycle Status Obsolete (legacy Altera MAX 9000 family) β€”
Usable Gates β€” 6,000 to 12,000
Macrocells β€” 560
User I/O Pins β€” 212
Pin-to-Pin Delay (tPD) β€” 20 ns
Maximum Counter Frequency β€” 144 MHz
Supply Voltage (VCC) β€” 4.75 V to 5.25 V
I/O Voltage β€” 3.3 V or 5 V (configurable)
In-System Programmability β€” Yes (5.0-V ISP via IEEE 1149.1 JTAG)
Package β€” 280-pin CPGA (Ceramic Pin Grid Array)
Configuration Memory β€” EEPROM (non-volatile, instant-on)
PCI Compliance β€” Yes
Operating Temperature β€” [DATA_NEEDED: industrial/commercial grade]

Datasheets & Resources

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