EPM9560R1208-20 vs EPM9560GC280-20 Comparaison
Comparaison détaillée côte à côte de EPM9560R1208-20 par Altera et EPM9560GC280-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560R1208-20 | EPM9560GC280-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $22,40 | $360,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks | 52 (typical for 560 macrocells) | — |
| Maximum User I/O | 212 | 212 |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Température de fonctionnement | 0C to +70C (commercial) | [DATA_NEEDED: commercial/industrial/military grade] |
| Boîtier | R-1208 (BGA-style fine-pitch) | 280-pin CPGA (Ceramic Pin Grid Array) |
| Type de montage | Surface Mount | Through-Hole (CPGA socket) |
| Process Technology | CMOS EEPROM, third-generation MAX architecture | CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) | — |
| Boundary-Scan Test | JTAG IEEE Std. 1149.1 | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Statut RoHS | [DATA_NEEDED: confirm via current distributor data] | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Counter Frequency (max) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| I/O Voltage | — | 3.3 V or 5.0 V configurable |
| In-System Programming | — | Yes, via IEEE 1149.1 JTAG |