EPM9560RC208-16 vs EPM9560RC208-15 Comparaison
Comparaison détaillée côte à côte de EPM9560RC208-16 par Intel et EPM9560RC208-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera
EPM9560RC208-16 NrndComparaison des spécifications
| Paramètre | EPM9560RC208-16 | EPM9560RC208-15 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $52,40 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Logic Elements / Macrocells | 560 macrocells | — |
| Typical Gates | 12,000 gates | — |
| Usable Gates | 12,000 (typical) | 12,000 gates |
| Pin-to-Pin Delay (tPD) | 16 ns | — |
| Maximum Internal Frequency (fMAX) | 117.6 MHz | — |
| Supply Voltage (VCCINT / VCCIO) | 5 V | — |
| User I/O Pins | 416 | — |
| Boîtier | 208-pin Power Quad Flat Pack (RQFP) | 208-pin RQFP (Power Quad Flat Pack) |
| Type de montage | Surface Mount | Surface Mount |
| Process Technology | 0.35 µm CMOS EEPROM | — |
| Programmability | In-system via JTAG (IEEE 1149.1) | — |
| Température de fonctionnement | [DATA_NEEDED: industrial/commercial temperature grade] | [DATA_NEEDED: operating temperature range] |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -16 | -15 (15 ns pin-to-pin) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Tension d'alimentation | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |