EPM9560RC240-12 vs EPM9560ARI240-10N Comparaison
Comparaison détaillée côte à côte de EPM9560RC240-12 par Altera et EPM9560ARI240-10N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM9560ARI240-10N - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
EPM9560ARI240-10N NrndComparaison des spécifications
| Paramètre | EPM9560RC240-12 | EPM9560ARI240-10N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $105,00 |
| Family | MAX 9000 (EPM9560) | MAX 9000 |
| Device Type | EE PLD / CPLD | — |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | — |
| User I/O Pins | 191 | — |
| Logic Array Blocks (LABs) | 20 | 16 |
| Maximum Propagation Delay (tPD) | 13.4 ns | — |
| Speed Grade | -12 (13.4 ns tPD) | — |
| Maximum Operating Frequency (estimated) | ~76 MHz registered | — |
| Core Supply Voltage (VCCINT) | 5 V | — |
| I/O Logic Levels | 3.3 V or 5 V (configurable) | — |
| Boîtier | PQFP-240 (RC240) 0.500 mm pitch, gull-wing | 240-pin RQFP (RQFP-240 / PQFP-240) |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Process Technology | CMOS | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | -40C to +85C (industrial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 12,000 |
| User I/Os | — | 216 (per digchip); 191 (per Mouser) |
| Maximum Internal Frequency | — | 144.9 MHz (typical); 145 MHz (per digchip) |
| Propagation Delay (tPD) | — | 10 ns (-10 speed grade) |
| Tension d'alimentation | — | 5.0 V nominal (4.5 V min, 5.5 V max) |
| Logic Family | — | CMOS, EEPROM-based |
| In-System Programmability | — | Yes (5.0 V ISP via JTAG) |
| Architecture | — | Multiple Array MatriX (MAX) - 3rd generation |
| JTAG (IEEE 1149.1) | — | Yes |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free / RoHS status not in provided data] |