EPM9560RC240-12 vs EPM9560ARI240-10N 对比

详细并排对比 EPM9560RC240-12 出自 Altera 和 EPM9560ARI240-10N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-12 EPM9560ARI240-10N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $9.95 $105.00
Family MAX 9000 (EPM9560) MAX 9000
Device Type EE PLD / CPLD —
Macrocells 560 560
Flip-Flops 772 —
User I/O Pins 191 —
Logic Array Blocks (LABs) 20 16
Maximum Propagation Delay (tPD) 13.4 ns —
Speed Grade -12 (13.4 ns tPD) —
Maximum Operating Frequency (estimated) ~76 MHz registered —
Core Supply Voltage (VCCINT) 5 V —
I/O Logic Levels 3.3 V or 5 V (configurable) —
封装 PQFP-240 (RC240) 0.500 mm pitch, gull-wing 240-pin RQFP (RQFP-240 / PQFP-240)
安装类型 Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) —
Programming Interface IEEE 1149.1 JTAG —
Process Technology CMOS —
工作温度 [DATA_NEEDED: operating temperature grade] -40C to +85C (industrial)
RoHS 状态 [DATA_NEEDED: RoHS compliance] —
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 12,000
User I/Os — 216 (per digchip); 191 (per Mouser)
Maximum Internal Frequency — 144.9 MHz (typical); 145 MHz (per digchip)
Propagation Delay (tPD) — 10 ns (-10 speed grade)
电源电压 — 5.0 V nominal (4.5 V min, 5.5 V max)
Logic Family — CMOS, EEPROM-based
In-System Programmability — Yes (5.0 V ISP via JTAG)
Architecture — Multiple Array MatriX (MAX) - 3rd generation
JTAG (IEEE 1149.1) — Yes
Lead-Free / RoHS — [DATA_NEEDED: lead-free / RoHS status not in provided data]

数据手册与资源

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