EPM9560RZ208-15 vs EPM9560RC208-15 Comparaison
Comparaison détaillée côte à côte de EPM9560RZ208-15 par Altera et EPM9560RC208-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560RZ208-15 | EPM9560RC208-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $55,00 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins (max) | 212 | — |
| Boîtier | RQFP-208 (PowerQuad QFP) | 208-pin RQFP (Power Quad Flat Pack) |
| Speed Grade | -15 (15 ns pin-to-pin delay) | -15 (15 ns pin-to-pin) |
| Process Technology | 0.35 µm CMOS EEPROM | — |
| Operating Voltage (Core) | 5.0 V | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fmax] | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | [DATA_NEEDED: temperature range] | [DATA_NEEDED: operating temperature range] |
| Statut RoHS | [DATA_NEEDED: RoHS] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Tension d'alimentation | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |