EPM9560WC208-15 vs EPM9560RC208-15N Comparaison
Comparaison détaillée côte à côte de EPM9560WC208-15 par Altera et EPM9560RC208-15N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP
EPM9560RC208-15N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM9560WC208-15 | EPM9560RC208-15N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $105,00 | $19,85 |
| Family | MAX 9000 | — |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Technology | CMOS | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 16 |
| Flip-Flops | 772 | — |
| User I/O Pins (max) | 149 | — |
| Fréquence d'horloge maximale | 117.6 MHz | — |
| Propagation Delay (tPD) | 16.6 ns | — |
| Speed Grade | -15 | -15 (15 ns tPD) |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | — |
| Boîtier | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | — |
| Type de montage | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| Statut RoHS | RoHS3 Compliant (per third-party listings) | [DATA_NEEDED: check part marking suffix for lead-free/RoHS] |
| Series | — | MAX 9000 |
| Usable Gates | — | 12,000 |
| User I/O | — | 212 (in 208-RQFP, see family datasheet) |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Internal Frequency | — | 117.6 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Configuration Memory | — | CMOS EEPROM (non-volatile) |
| Operating Temperature (commercial) | — | 0C to +70C |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |