EPM9560WC208-15 vs EPM9560WI208-20 Comparaison
Comparaison détaillée côte à côte de EPM9560WC208-15 par Altera et EPM9560WI208-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560WC208-15 | EPM9560WI208-20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $105,00 | $105,00 |
| Family | MAX 9000 | — |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | EE PLD / Complex Programmable Logic Device (CPLD) |
| Technology | CMOS | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 35 | 16 |
| Flip-Flops | 772 | — |
| User I/O Pins (max) | 149 | — |
| Fréquence d'horloge maximale | 117.6 MHz | — |
| Propagation Delay (tPD) | 16.6 ns | — |
| Speed Grade | -15 | -20 |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | — |
| Boîtier | 208-pin CQFP (Ceramic Quad Flat Pack) | — |
| Terminal Pitch | 0.50 mm | — |
| Type de montage | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| Statut RoHS | RoHS3 Compliant (per third-party listings) | — |
| Device Family | — | MAX 9000 |
| Macrocells / Logic Cells | — | 560 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Propagation Delay (tPD) | — | 23.6 ns |
| Process Technology | — | 0.35 micron CMOS EEPROM |
| Programmability | — | In-system via JTAG (IEEE 1149.1) |
| Package Type | — | CQFP-208 (Ceramic Quad Flat Pack) |
| Terminal Form | — | Gull Wing |
| Number of Terminals | — | 208 |
| Package Code | — | QFP |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Industrial |
| Design Tools | — | MAX+PLUS II, Quartus |
| Compliance | — | [DATA_NEEDED: RoHS status] |