EPM9560WC208-15 vs EPM9560WI208-20 Comparison
Detailed side-by-side comparison of EPM9560WC208-15 by Altera and EPM9560WI208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560WC208-15 | EPM9560WI208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $105.00 | $105.00 |
| Family | MAX 9000 | β |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | EE PLD / Complex Programmable Logic Device (CPLD) |
| Technology | CMOS | β |
| Macrocells | 560 | β |
| Logic Array Blocks (LABs) | 35 | 16 |
| Flip-Flops | 772 | β |
| User I/O Pins (max) | 149 | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Propagation Delay (tPD) | 16.6 ns | β |
| Speed Grade | -15 | -20 |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | β |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | β |
| Terminal Pitch | 0.50 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | β |
| RoHS Status | RoHS3 Compliant (per third-party listings) | β |
| Device Family | β | MAX 9000 |
| Macrocells / Logic Cells | β | 560 |
| Maximum User I/O Pins | β | 212 |
| Pin-to-Pin Propagation Delay (tPD) | β | 23.6 ns |
| Process Technology | β | 0.35 micron CMOS EEPROM |
| Programmability | β | In-system via JTAG (IEEE 1149.1) |
| Package Type | β | CQFP-208 (Ceramic Quad Flat Pack) |
| Terminal Form | β | Gull Wing |
| Number of Terminals | β | 208 |
| Package Code | β | QFP |
| Package Shape | β | Square |
| Operating Temperature Grade | β | Industrial |
| Design Tools | β | MAX+PLUS II, Quartus |
| Compliance | β | [DATA_NEEDED: RoHS status] |