M7AFS600-FGG484I vs AFS600-FGG484 Comparaison
Comparaison détaillée côte à côte de M7AFS600-FGG484I par Microchip Technology et AFS600-FGG484 par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
M7AFS600-FGG484I - Fusion FPGA 600K Gates 484-BGA | Microchip
M7AFS600-FGG484I ✓ Actif
Comparaison des spécifications
| Paramètre | M7AFS600-FGG484I | AFS600-FGG484 |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $219,20 | $0,00 |
| Programmable Logic Family | Fusion (Microsemi/Actel, now Microchip) | — |
| System Gates | 600000 gates | 600000 gates |
| Embedded Processor | ARM CoreMP7 (ARM7TDMI-compatible) | — |
| User I/O | 172 I/O | — |
| Configuration Technology | Flash-based, on-chip | — |
| Core Supply Voltage | 1.5 V | — |
| Boîtier | 484-BGA (FGG484), 1.0 mm ball pitch | 484-pin FBGA; one verified source alternatively labels BGA-256 |
| Type de montage | Surface Mount | Surface mount |
| Température de fonctionnement | -40C to +100C (industrial, I grade) | 0 C to 70 C |
| Memory - Listable Resource | 110592 (per DigiKey listing) | — |
| Maximum Operating Frequency | [DATA_NEEDED: maximum operating frequency] | — |
| I/O Bank Count | [DATA_NEEDED: I/O bank count] | — |
| Embedded Flash Blocks | [DATA_NEEDED: embedded flash block count] | — |
| Analog Peripherals | [DATA_NEEDED: analog peripheral configuration] | — |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Programming Tool Chain | Microchip Libero SoC (formerly Actel Libero) | — |
| Device Type | — | Fusion mixed-signal FPGA |
| Maximum Frequency | — | 1098.9 MHz |
| Technology | — | 130 nm |
| Metal Layers | — | 7 layers |
| Process | — | Flash-based CMOS |
| Tension d'alimentation | — | 1.5 V |
| I/O Count | — | 172 I/O |
| Configuration Retention | — | Nonvolatile flash |
| Power-Up Feature | — | Live at Power-Up (LAPU) |
| Architecture | — | Monolithic mixed-signal FPGA |
| Programmable Logic | — | High-performance flash-based programmable logic |
| Analog Resources | — | Configurable analog resources |
| Flash Memory | — | Large flash-memory blocks |
| Clocking | — | Comprehensive clock generation and management circuitry |
| Processor Support | — | Optional ARM support |
| Statut du cycle de vie | — | [DATA_NEEDED: current lifecycle status] |
| RoHS Compliance | — | [DATA_NEEDED: RoHS compliance status] |
| REACH Compliance | — | [DATA_NEEDED: REACH compliance status] |