MC68360VR33L vs MC68EN360VR33L Comparaison
Comparaison détaillée côte à côte de MC68360VR33L par NXP Semiconductors et MC68EN360VR33L par NXP Semiconductors. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
NXP Semiconductors
MC68EN360VR33L - 33MHz M683xx QUICC CPU32+ MPU, 357-PBGA | NXP
MC68EN360VR33L ✗ Fin de vieComparaison des spécifications
| Paramètre | MC68360VR33L | MC68EN360VR33L |
|---|---|---|
| Marque | NXP Semiconductors | NXP Semiconductors |
| Catégorie | Microcontrollers | Microcontrollers |
| Statut du cycle de vie | NRND | Fin de vie |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $44,10 | $78,95 |
| Core | CPU32+ (M683xx) | — |
| Number of Cores | 1 | — |
| Largeur du bus de données | 32 bit | 32-bit |
| Fréquence d'horloge maximale | 33 MHz | — |
| Tension d'alimentation | 5 V | 5 V |
| Instruction Cache | 4 Kbytes | — |
| Serial Communication Controllers (SCC) | 4 (HDLC/UART/transparent/BISYNC) | — |
| On-chip Communications Processor Module | Yes (CPM, RISC) | — |
| System Integration Module | SIM40 | — |
| Boîtier | 357-PBGA 25x25 mm | 357-Ball PBGA, 25x25 mm, 1.27 mm pitch ('VR') |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | -40C to +85C (industrial) |
| Packaging | Tray | Tray |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Series | MC68360 QUICC | — |
| Sub-series | SIM 4SCC | — |
| Processor Type | — | M683xx 32-bit CPU32+ |
| Core Architecture | — | CPU32+ with QUICC RISC communications engine |
| Core Count | — | 1 |
| Bus Speed / Operating Frequency | — | 33 MHz |
| Address Bus Width | — | 32-bit (4 GB space) |
| Ethernet MAC | — | Integrated 10/100 Ethernet (MII interface) - 'EN' suffix |
| Serial Communication Channels (SCC) | — | 4 (per QUICC engine) |
| DMA Channels | — | 2 (per QUICC engine) |
| Timers | — | 4 general-purpose 16-bit timers |
| DRAM Controller | — | Integrated, supports FPM/EDO DRAM |
| Interrupt Controller | — | Integrated, programmable priority |
| Instruction Set | — | M68k (CPU32+) binary-compatible |
| Lead Free / RoHS | — | Lead Free / RoHS Compliant |
| Process Technology | — | 0.57 um CMOS (per Freescale datasheet) |