MC68360VR33L vs MC68EN360VR33L Comparación
Comparación detallada lado a lado de MC68360VR33L por NXP Semiconductors y MC68EN360VR33L por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
MC68EN360VR33L - 33MHz M683xx QUICC CPU32+ MPU, 357-PBGA | NXP
MC68EN360VR33L ✗ Fin de vidaComparación de especificaciones
| Parámetro | MC68360VR33L | MC68EN360VR33L |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | NRND | Fin de vida |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $44,10 | $78,95 |
| Core | CPU32+ (M683xx) | — |
| Number of Cores | 1 | — |
| Ancho del bus de datos | 32 bit | 32-bit |
| Frecuencia de reloj máxima | 33 MHz | — |
| Tensión de alimentación | 5 V | 5 V |
| Instruction Cache | 4 Kbytes | — |
| Serial Communication Controllers (SCC) | 4 (HDLC/UART/transparent/BISYNC) | — |
| On-chip Communications Processor Module | Yes (CPM, RISC) | — |
| System Integration Module | SIM40 | — |
| Encapsulado | 357-PBGA 25x25 mm | 357-Ball PBGA, 25x25 mm, 1.27 mm pitch ('VR') |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature grade] | -40C to +85C (industrial) |
| Packaging | Tray | Tray |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Series | MC68360 QUICC | — |
| Sub-series | SIM 4SCC | — |
| Processor Type | — | M683xx 32-bit CPU32+ |
| Core Architecture | — | CPU32+ with QUICC RISC communications engine |
| Core Count | — | 1 |
| Bus Speed / Operating Frequency | — | 33 MHz |
| Address Bus Width | — | 32-bit (4 GB space) |
| Ethernet MAC | — | Integrated 10/100 Ethernet (MII interface) - 'EN' suffix |
| Serial Communication Channels (SCC) | — | 4 (per QUICC engine) |
| DMA Channels | — | 2 (per QUICC engine) |
| Timers | — | 4 general-purpose 16-bit timers |
| DRAM Controller | — | Integrated, supports FPM/EDO DRAM |
| Interrupt Controller | — | Integrated, programmable priority |
| Instruction Set | — | M68k (CPU32+) binary-compatible |
| Lead Free / RoHS | — | Lead Free / RoHS Compliant |
| Process Technology | — | 0.57 um CMOS (per Freescale datasheet) |