MM74C948N vs ADC0809CCN Comparaison
Comparaison détaillée côte à côte de MM74C948N par Texas Instruments et ADC0809CCN par Texas Instruments. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Texas Instruments
MM74C948N - 8-Bit ADC w/ 16-Ch MUX | Texas Instruments | DIP-40
MM74C948N Obsolete
Comparaison des spécifications
| Paramètre | MM74C948N | ADC0809CCN |
|---|---|---|
| Marque | Texas Instruments | Texas Instruments |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Obsolete | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,05 | $3,40 |
| Résolution | 8 bit | 8 bits |
| Architecture | Successive Approximation (SAR) | Successive Approximation (SAR) |
| Number of Analog Input Channels | 16 (single-ended, multiplexed) | — |
| Tension d'alimentation | 5 V (single supply) | — |
| Maximum Conversion Time | 116 us | — |
| Technology | CMOS | — |
| Interface | Microprocessor-compatible parallel | — |
| Température de fonctionnement | -40C to +85C | -40 °C to +85 °C |
| Temperature Grade | Industrial | — |
| Boîtier | PDIP-40 (N) | 28-pin PDIP (through-hole) |
| Type de montage | Through-Hole | Through-Hole (DIP) |
| Terminal Form | Through-Hole | — |
| Package Code | DIP | — |
| Number of Terminals | 40 | — |
| Package Shape | Rectangular | — |
| Statut RoHS | [DATA_NEEDED: RoHS status - datasheet predates RoHS era] | Compliant (NOPB variant); non-compliant legacy |
| Number of Channels | — | 8 single-ended |
| Sample Rate (max) | — | 10 kSPS |
| Input Type | — | Single-Ended, Multiplexed |
| Supply Voltage (VCC) | — | 4.5 V to 5.25 V (5 V typical) |
| Courant d'alimentation | — | [DATA_NEEDED: typical quiescent current] |
| Analog Input Voltage Range | — | 0 V to VCC |
| Integral Nonlinearity (INL) | — | ±1 LSB max |
| Differential Nonlinearity (DNL) | — | ±1 LSB max (no missing codes) |
| Conversion Time (typ) | — | [DATA_NEEDED: at fCLK] |
| Clock Frequency | — | 10 kHz to 1.1 MHz |
| Tension de référence | — | Internal 256R ladder, VREF+ / VREF- pins |
| Digital I/O Logic Level | — | TTL/CMOS compatible |
| Output Interface | — | 8-bit parallel, tri-state latched |
| Channel Selection | — | 3-bit address latch (A0/A1/A2) |