MPC8247CZQTIEA vs MPC8247CVRTIEA557 Comparaison
Comparaison détaillée côte à côte de MPC8247CZQTIEA par NXP Semiconductors et MPC8247CVRTIEA557 par NXP Semiconductors. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
NXP Semiconductors
MPC8247CZQTIEA - PowerQUICC II 400MHz MPU, 516-PBGA | NXP
MPC8247CZQTIEA ✗ Fin de vieNXP Semiconductors
MPC8247CVRTIEA557 - PowerQUICC II 400MHz MPU, PBGA-516 | NXP
MPC8247CVRTIEA557 NrndComparaison des spécifications
| Paramètre | MPC8247CZQTIEA | MPC8247CVRTIEA557 |
|---|---|---|
| Marque | NXP Semiconductors | NXP Semiconductors |
| Catégorie | Microcontrollers | Microcontrollers |
| Statut du cycle de vie | Fin de vie | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $27,85 | $1,65 |
| Manufacturer | NXP Semiconductors | NXP Semiconductors |
| Series | PowerQUICC II | — |
| Core Processor | PowerPC G2_LE | — |
| Core Architecture | 32-bit Power Architecture | PowerPC G2_LE |
| Core Count | 1 | 1 |
| Core Speed | 400 MHz | — |
| Boîtier | 516-PBGA (TEPBGA) 27x27 mm | 516-ball PBGA, 27x27 mm |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Température de fonctionnement | -40C to +105C (Industrial) | — |
| Tension d'alimentation | 3.3 V core/IO | — |
| Process Technology | 0.13 um CMOS | — |
| Integrated Peripherals | CPM, PCI 2.2, USB 1.1, 2x 10/100 Ethernet MAC | — |
| SDRAM Controller | PC-133 SDRAM, 32-bit data | — |
| DMA Channels | 4 | — |
| Ethernet | Dual 10/100 MII/RMII MAC | Dual 10/100 Mbps Fast Ethernet MACs (via CPM) |
| Statut RoHS | Compliant | Compliant |
| Niveau MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL level] |
| Lifecycle | End of Life (per NXP product page) | — |
| Product Family | — | PowerQUICC II (MPC82xx) |
| Bit Width | — | 32-bit |
| Maximum Core Frequency | — | 400 MHz |
| Plage de température de fonctionnement | — | -40 C to +105 C |
| Package Family | — | PBGA (Plastic Ball Grid Array) |
| Communications Processor Module (CPM) | — | Yes (integrated, with PCI, USB, Fast Ethernet MACs) |
| PCI Interface | — | 32-bit, up to 66 MHz |
| USB Interface | — | USB 1.1 (host and slave) |
| L1 Cache | — | 16 KB unified instruction/data |
| Lead-Free | — | Yes |
| AEC-Q100 | — | Not qualified |
| DDR Memory Controller | — | [DATA_NEEDED: DDR generation and width] |