MPC8548VTAQGB vs P2020NXE2HHC Comparaison
Comparaison détaillée côte à côte de MPC8548VTAQGB par NXP Semiconductors et P2020NXE2HHC par NXP Semiconductors. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
NXP Semiconductors
P2020NXE2HHC - QorIQ Dual-Core 1.2GHz Power Arch SoC | NXP
P2020NXE2HHC ⚠ Dernier achatComparaison des spécifications
| Paramètre | MPC8548VTAQGB | P2020NXE2HHC |
|---|---|---|
| Marque | NXP Semiconductors | NXP Semiconductors |
| Catégorie | Microcontrollers | Microcontrollers |
| Statut du cycle de vie | Actif | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $340,00 | $192,40 |
| Core Architecture | PowerPC e500 | Power Architecture e500v2, dual-core |
| Processor Series | MPC8548 (PowerQUICC III / MPC85xx) | — |
| Number of Cores | 1 | — |
| Largeur du bus de données | 32-bit | — |
| Maximum Core Frequency | 1.0 GHz | — |
| Process Technology | 90 nm CMOS | 45nm |
| Core Supply Voltage | 1.1 V | — |
| I/O Supply Voltages | 1.8 V / 2.5 V / 3.3 V | — |
| Boîtier / Format | 783-FCBGA (29 x 29 mm) | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Température de fonctionnement | 0C to +105C (commercial extended, TBD - confirm from datasheet) | -40C to +125C |
| On-chip SRAM (L2) | [DATA_NEEDED: L2 cache size] | — |
| Memory Controller | Dual DDR1/DDR2 with ECC | DDR2/DDR3 with ECC support |
| Gigabit Ethernet MACs | 4x tri-speed (10/100/1000) | — |
| XAUI / SerDes | Up to 4x XAUI / SGMII lanes | — |
| Security Engine | Integrated IPsec/SSL/SRNG | SEC 4.0 (IPsec/SSL/3GPP acceleration) |
| PCI Express | Multiple x1/x2/x4 interfaces | 3x PCIe Gen 1/Gen 2 controllers |
| Statut RoHS | Compliant (Pb-free) | RoHS Compliant |
| Processor Type | — | PowerPC e500v2 Microprocessor IC QorIQ P2 |
| Core Count | — | 2 |
| Operating Frequency | — | 1.2 GHz (800 MHz/800 MHz core config per NXP marketing code) |
| L1 Cache | — | 32 KB instruction + 32 KB data per core |
| L2 Cache | — | 256 KB unified |
| Ethernet | — | 3x Gigabit Ethernet with IEEE 1588 |
| Serial RapidIO | — | 2x SRIO ports |
| USB | — | 2x USB 2.0 with integrated PHY |
| Boîtier | — | 689-TEPBGA II (31x31 mm) |
| Lead Free Status | — | Lead Free |
| Revision | — | R2.1 |