MPC8548VTAQGB vs P2020NXE2HHC 比較
詳細な並列比較: MPC8548VTAQGB メーカー: NXP Semiconductors および P2020NXE2HHC メーカー: NXP Semiconductors。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
NXP Semiconductors
P2020NXE2HHC - QorIQ Dual-Core 1.2GHz Power Arch SoC | NXP
P2020NXE2HHC ⚠ ラストタイムバイ仕様比較
| パラメータ | MPC8548VTAQGB | P2020NXE2HHC |
|---|---|---|
| ブランド | NXP Semiconductors | NXP Semiconductors |
| カテゴリ | Microcontrollers | Microcontrollers |
| ライフサイクル状態 | 有効 | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $340.00 | $192.40 |
| Core Architecture | PowerPC e500 | Power Architecture e500v2, dual-core |
| Processor Series | MPC8548 (PowerQUICC III / MPC85xx) | — |
| Number of Cores | 1 | — |
| データバス幅 | 32-bit | — |
| Maximum Core Frequency | 1.0 GHz | — |
| Process Technology | 90 nm CMOS | 45nm |
| Core Supply Voltage | 1.1 V | — |
| I/O Supply Voltages | 1.8 V / 2.5 V / 3.3 V | — |
| パッケージ / ケース | 783-FCBGA (29 x 29 mm) | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount (BGA) |
| 動作温度 | 0C to +105C (commercial extended, TBD - confirm from datasheet) | -40C to +125C |
| On-chip SRAM (L2) | [DATA_NEEDED: L2 cache size] | — |
| Memory Controller | Dual DDR1/DDR2 with ECC | DDR2/DDR3 with ECC support |
| Gigabit Ethernet MACs | 4x tri-speed (10/100/1000) | — |
| XAUI / SerDes | Up to 4x XAUI / SGMII lanes | — |
| Security Engine | Integrated IPsec/SSL/SRNG | SEC 4.0 (IPsec/SSL/3GPP acceleration) |
| PCI Express | Multiple x1/x2/x4 interfaces | 3x PCIe Gen 1/Gen 2 controllers |
| RoHS ステータス | Compliant (Pb-free) | RoHS Compliant |
| Processor Type | — | PowerPC e500v2 Microprocessor IC QorIQ P2 |
| Core Count | — | 2 |
| Operating Frequency | — | 1.2 GHz (800 MHz/800 MHz core config per NXP marketing code) |
| L1 Cache | — | 32 KB instruction + 32 KB data per core |
| L2 Cache | — | 256 KB unified |
| Ethernet | — | 3x Gigabit Ethernet with IEEE 1588 |
| Serial RapidIO | — | 2x SRIO ports |
| USB | — | 2x USB 2.0 with integrated PHY |
| パッケージ | — | 689-TEPBGA II (31x31 mm) |
| Lead Free Status | — | Lead Free |
| Revision | — | R2.1 |