MPC859TVR100A vs MPC859TCVR100A Comparaison
Comparaison détaillée côte à côte de MPC859TVR100A par NXP Semiconductors et MPC859TCVR100A par NXP Semiconductors. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | MPC859TVR100A | MPC859TCVR100A |
|---|---|---|
| Marque | NXP Semiconductors | NXP Semiconductors |
| Catégorie | Microcontrollers | Microcontrollers |
| Statut du cycle de vie | NRND | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $21,65 | $42,45 |
| Processor Series | MPC8xx PowerQUICC | — |
| Core Architecture | 32-bit Power Architecture | — |
| Core Count | 1 | — |
| Core Frequency | 100 MHz | 100 MHz |
| Operating Voltage (Core) | 1.8 V | [DATA_NEEDED: core VDD] |
| Operating Voltage (I/O) | 3.3 V | [DATA_NEEDED: I/O VDD] |
| Process Technology | 0.18 µm CMOS | [DATA_NEEDED: process node] |
| Boîtier | 357-PBGA (25 mm x 25 mm) | 357-PBGA (25x25 mm) |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Température de fonctionnement | 0 °C to +95 °C | -40C to +100C |
| Integrated Module | CPM (Communications Processor Module) | — |
| Serial Interfaces | SCC, FCC, SPI, I2C (via CPM) | — |
| Largeur du bus de données | 32-bit | — |
| Statut RoHS | Compliant | [DATA_NEEDED: lead-free/RoHS status] |
| Lead-Free Status | Lead Free | — |
| Packaging | Tray | — |
| Architecture | — | 32-bit Power Architecture (PowerPC 8xx family) |
| Core | — | MPC8xx 1 Core, 32-Bit |
| Instruction Set | — | PowerPC |
| Memory Controller | — | 8/16/32-bit ROM/FLASH/SRAM/DRAM |
| Communications Processor Module | — | Yes (CPM with serial channels) |
| Local Bus | — | 32-bit PC-AT ISA-style (M68000 bus compatible) |
| PCMCIA Interface | — | Yes, 2 card slots supported |
| Timers | — | Four 16-bit timers |
| Interrupt Controller | — | Integrated in SIU |
| DMA | — | Integrated in CPM (peripheral DMA) |